1. Field of the Invention
The present invention is related to a circuit for simultaneously analyzing performance and bugs and related method thereof, and particularly to a circuit and method thereof that can utilize packets of a USB 3.0 bus to simultaneously analyze performance and bugs.
2. Description of the Prior Art
In the prior art, a user has to observe data transmission conditions between a USB 3.0 host and a USB 3.0 device through a USB 3.0 data flow analyzer, and determine how much time is spent by the USB 3.0 host to execute commands to analyze performance of the USB 3.0 host through a data flow analyzer of a peripheral component interconnect express (PCIE) interface after the USB 3.0 host receives the commands transmitted by the peripheral component interconnect express interface. In addition, when the user analyzes bugs of the USB 3.0 host, the user usually needs to analyze data transmitted between the USB 3.0 host and the USB 3.0 device, and data in the peripheral component interconnect express interface to discover the bugs of the USB 3.0 host. However, the prior art utilizes an artificial method to simultaneously execute the abovementioned operation for analyzing the performance of the USB 3.0 host and the bugs of the USB 3.0 host. Therefore, the prior art not only spends more time and has lower efficiency, but also needs the USB 3.0 data flow analyzer and the data flow analyzer of the peripheral component interconnect express interface to simultaneously work on analyzing the performance of the USB 3.0 host and the bugs of the USB 3.0 host.